As a kind of flat-panel display device, thin film transistor liquid crystal displays (TFT-LCDs) have been increasingly applied in the field of high-performance display due to such features as small volume, low power consumption, being free of radiation and low production cost.
As shown in FIG. 1, the TFT-LCD includes an active area (AA) and an inactive area. Within the active area, there is a plurality of subpixels 10 arranged in a matrix form and defined by a plurality of gate lines (G1, G2, G3, . . . , Gi, . . . , Gn) and a plurality of data lines (D1, D2, D3, . . . , Dj, . . . Dm) crossing each other. Within the inactive area, there is a timing controller 11, a gate driver 12 and a source driver 13.
The timing controller 11 is configured to output a gate driver start signal (STV) to the gate driver 12, and then the received STV is shifted level by level through a shift register 120, so as to output a scanning signal. A level shifter 121 receives the scanning signal and determines whether or not to output the scanning signal to the gate line (e.g., Gi) in accordance with a signal, i.e., Output Enable signal. Meanwhile, the timing controller 11 outputs a source driver start signal (STH), a digital data (DD) signal and a latch input (LP) signal to the source driver 13. In a latch 130, the DD signal is latched by the STH into a corresponding channel, and whether or not to output the DD signal to the data line (e.g., Dj) is determined in accordance with the LP signal. Then, the DD signal is converted into a data signal Vdata via a digital-to-analog converter 131. When the gate lines are turned on progressively, the data signal Vdata is inputted into the corresponding data line, so as to display an image.
However, for an existing display with high pixels per inch (PPI), there are a large number of subpixels 10, so a large number of gate lines are required. In this case, when the gate lines (G1, G2, G3, . . . , Gi, . . . Gn) are turned on progressively, there is a delay for the subpixels 10 in a row, which are turned on late, to receive the data signal Vdata from the data line (D1, D2, D3, . . . , Dj, . . . Dm). As a result, a response speed for the display will be reduced, and thereby the display quality of the display with high PPI will be adversely affected.